Advancements in Integrated Circuit (IC) technology has led to smaller and more fragile active devices with thinner gate oxide layers to achieve higher operation speed and lower power consumption. With aggressive scaling down of the transistor size, the electrostatic discharge (ESD) has not scaled down with CMOS technology, and thus ESD protection design in nanoscale CMOS processes becomes a challenging task. Due to the large number of transistors placed on an IC, the technology is driven by the need to reduce power consumption and maintain high reliability.
In a system on chip (SoC) design, different blocks such as digital and analog are fabricated onto a single IC, and hence requires different voltages to achieve reduced power consumption and optimum performance. As a result, a level shifter is widely used to convert a logic signal from one voltage level to another voltage level. Therefore, in multi domain high speed applications (like USB 3.0, Thunder Bolt etc), ESD protection in a level shifter at the domain interface is very crucial and imposes several challenges due to low oxide breakdown voltage. Existing level shifter designs are susceptible to ESD failures in advanced CMOS nodes and hence there is a need for a level shifter with improved ESD protection without compromising on the robustness.